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Digital Systems –
Medium Difficulty
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#1. Convert decimal 96 to binary.
#2. Convert binary 111001 to decimal.
#3. What is the 8-bit two’s complement representation of decimal -97?
#4. Convert hexadecimal A5 to decimal.
#5. How many distinct unsigned values can be represented with 6 bits?
#6. Convert decimal 124 to binary.
#7. Convert binary 1001101 to decimal.
#8. What is the 8-bit two’s complement representation of decimal -47?
#9. Convert hexadecimal 3A to decimal.
#10. How many distinct unsigned values can be represented with 6 bits?
#11. Convert decimal 170 to binary.
#12. Convert binary 111001 to decimal.
#13. What is the 8-bit two’s complement representation of decimal -118?
#14. Simplify Boolean expression F = A’B + AB.
#15. What is the value of A + A’ in Boolean algebra?
#16. By DeMorgan’s law, (AB)’ equals:
#17. Which operation is represented by โ in digital logic?
#18. Simplify Boolean expression F = A’B + AB.
#19. What is the value of A + A’ in Boolean algebra?
#20. By DeMorgan’s law, (AB)’ equals:
#21. Which operation is represented by โ in digital logic?
#22. Simplify Boolean expression F = A’B + AB.
#23. What is the value of A + A’ in Boolean algebra?
#24. By DeMorgan’s law, (AB)’ equals:
#25. Which operation is represented by โ in digital logic?
#26. Simplify Boolean expression F = A’B + AB.
#27. A NAND gate is followed by an inverter. The overall function is:
#28. How many select lines are required for an 8-to-1 multiplexer?
#29. A half-adder produces which outputs?
#30. What is the output of an OR gate when both inputs are 0?
#31. A NAND gate is followed by an inverter. The overall function is:
#32. How many select lines are required for an 8-to-1 multiplexer?
#33. A half-adder produces which outputs?
#34. What is the output of an OR gate when both inputs are 0?
#35. A NAND gate is followed by an inverter. The overall function is:
#36. How many select lines are required for an 8-to-1 multiplexer?
#37. A half-adder produces which outputs?
#38. What is the output of an OR gate when both inputs are 0?
#39. A NAND gate is followed by an inverter. The overall function is:
#40. For F(A,B) = ฮฃm(1,2,3), what is the simplified expression?
#41. For 3-variable K-map with ones at m(0,1,2,3), simplified F is:
#42. In K-map grouping, legal group sizes are powers of:
#43. What is the main goal of Karnaugh-map simplification?
#44. For F(A,B) = ฮฃm(1,2,3), what is the simplified expression?
#45. For 3-variable K-map with ones at m(0,1,2,3), simplified F is:
#46. In K-map grouping, legal group sizes are powers of:
#47. What is the main goal of Karnaugh-map simplification?
#48. For F(A,B) = ฮฃm(1,2,3), what is the simplified expression?
#49. For 3-variable K-map with ones at m(0,1,2,3), simplified F is:
#50. In K-map grouping, legal group sizes are powers of:
#51. What is the main goal of Karnaugh-map simplification?
#52. For F(A,B) = ฮฃm(1,2,3), what is the simplified expression?
#53. Which flip-flop toggles output when J=K=1 at the active clock edge?
#54. Minimum number of flip-flops required for a MOD-12 counter is:
#55. In a D flip-flop, the next state Q(n+1) equals:
#56. An asynchronous ripple counter compared with a synchronous counter generally has:
#57. What is the output frequency of the LSB stage of a binary counter relative to input clock?
#58. Which flip-flop toggles output when J=K=1 at the active clock edge?
#59. Minimum number of flip-flops required for a MOD-12 counter is:
#60. In a D flip-flop, the next state Q(n+1) equals:
#61. An asynchronous ripple counter compared with a synchronous counter generally has:
#62. What is the output frequency of the LSB stage of a binary counter relative to input clock?
#63. Which flip-flop toggles output when J=K=1 at the active clock edge?
#64. Minimum number of flip-flops required for a MOD-10 counter is:
#65. A PLA/PLD is primarily used to implement:
#66. In FSM design, the state register is typically implemented with:
#67. A synchronous path has tCQ=1.5 ns, logic delay=4.0 ns, setup=1.0 ns. Approximate maximum clock frequency.
#68. In a Moore machine, outputs depend on:
#69. What is the main purpose of a timing diagram in digital design?
#70. A PLA/PLD is primarily used to implement:
#71. In FSM design, the state register is typically implemented with:
#72. A synchronous path has tCQ=1.0 ns, logic delay=3.0 ns, setup=2.0 ns. Approximate maximum clock frequency.
#73. In a Moore machine, outputs depend on:
#74. What is the main purpose of a timing diagram in digital design?
#75. A PLA/PLD is primarily used to implement:
#76. In FSM design, the state register is typically implemented with:
#77. Which flip-flop toggles output when J=K=1 at the active clock edge?
#78. Minimum number of flip-flops required for a MOD-10 counter is:
#79. In a D flip-flop, the next state Q(n+1) equals:
#80. An asynchronous ripple counter compared with a synchronous counter generally has:
#81. What is the output frequency of the LSB stage of a binary counter relative to input clock?
#82. Which flip-flop toggles output when J=K=1 at the active clock edge?
#83. Minimum number of flip-flops required for a MOD-12 counter is:
#84. In a D flip-flop, the next state Q(n+1) equals:
#85. An asynchronous ripple counter compared with a synchronous counter generally has:
#86. What is the output frequency of the LSB stage of a binary counter relative to input clock?
#87. Which flip-flop toggles output when J=K=1 at the active clock edge?
#88. Minimum number of flip-flops required for a MOD-12 counter is:
#89. A PLA/PLD is primarily used to implement:
#90. In FSM design, the state register is typically implemented with:
#91. A synchronous path has tCQ=1.0 ns, logic delay=5.0 ns, setup=1.5 ns. Approximate maximum clock frequency.
#92. In a Moore machine, outputs depend on:
#93. What is the main purpose of a timing diagram in digital design?
#94. A PLA/PLD is primarily used to implement:
#95. In FSM design, the state register is typically implemented with:
#96. A synchronous path has tCQ=1.5 ns, logic delay=3.0 ns, setup=1.5 ns. Approximate maximum clock frequency.
#97. In a Moore machine, outputs depend on:
#98. What is the main purpose of a timing diagram in digital design?
#99. A PLA/PLD is primarily used to implement:
#100. In FSM design, the state register is typically implemented with:
