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Digital Systems –
High Difficulty
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#1. In 8-bit signed two’s complement, what is the result of 91 + 91?
#2. For 8-bit arithmetic, compute hexadecimal 4B + 1F.
#3. An unsigned ADC has 12 bits and LSB size 2.5 mV. What is maximum representable input (full-scale minus 1 LSB)?
#4. Why is Gray code often used at mechanical encoder interfaces?
#5. For signed-magnitude and two’s complement, which statement is correct?
#6. In 8-bit signed two’s complement, what is the result of 109 + 109?
#7. For 8-bit arithmetic, compute hexadecimal 95 + 1F.
#8. An unsigned ADC has 8 bits and LSB size 2.5 mV. What is maximum representable input (full-scale minus 1 LSB)?
#9. Why is Gray code often used at mechanical encoder interfaces?
#10. For signed-magnitude and two’s complement, which statement is correct?
#11. In 8-bit signed two’s complement, what is the result of 58 + 58?
#12. For 8-bit arithmetic, compute hexadecimal 95 + 33.
#13. An unsigned ADC has 10 bits and LSB size 1 mV. What is maximum representable input (full-scale minus 1 LSB)?
#14. Simplify F = A’BC + ABC + AB’C using Boolean algebra.
#15. Given F = (A + B)(A + B’), the minimal form is:
#16. Which expression correctly implements XOR using only AND/OR/NOT?
#17. A static-1 hazard is most likely when:
#18. Simplify F = A’BC + ABC + AB’C using Boolean algebra.
#19. Given F = (A + B)(A + B’), the minimal form is:
#20. Which expression correctly implements XOR using only AND/OR/NOT?
#21. A static-1 hazard is most likely when:
#22. Simplify F = A’BC + ABC + AB’C using Boolean algebra.
#23. Given F = (A + B)(A + B’), the minimal form is:
#24. Which expression correctly implements XOR using only AND/OR/NOT?
#25. A static-1 hazard is most likely when:
#26. Simplify F = A’BC + ABC + AB’C using Boolean algebra.
#27. A ripple-carry adder has 8 full-adder stages. Worst-case carry propagation traverses how many stages?
#28. Compared with ripple-carry architecture, carry-lookahead adders primarily improve:
#29. A combinational circuit has fan-in constraints and heavy loading. Which design change most directly addresses excessive propagation delay?
#30. In synchronous design, why are purely combinational feedback loops avoided?
#31. A ripple-carry adder has 16 full-adder stages. Worst-case carry propagation traverses how many stages?
#32. Compared with ripple-carry architecture, carry-lookahead adders primarily improve:
#33. A combinational circuit has fan-in constraints and heavy loading. Which design change most directly addresses excessive propagation delay?
#34. In synchronous design, why are purely combinational feedback loops avoided?
#35. A ripple-carry adder has 16 full-adder stages. Worst-case carry propagation traverses how many stages?
#36. Compared with ripple-carry architecture, carry-lookahead adders primarily improve:
#37. A combinational circuit has fan-in constraints and heavy loading. Which design change most directly addresses excessive propagation delay?
#38. In synchronous design, why are purely combinational feedback loops avoided?
#39. A ripple-carry adder has 4 full-adder stages. Worst-case carry propagation traverses how many stages?
#40. Minimize F(A,B,C,D) = ฮฃm(0,2,8,10).
#41. For F(A,B,C,D)=ฮฃm(1,3,9,11,5,7,13,15), the minimal SOP is:
#42. When using don’t-care terms in 4-variable K-maps, best practice is to:
#43. A minimized SOP misses a consensus term between adjacent implicants. What issue is most likely in real hardware?
#44. Minimize F(A,B,C,D) = ฮฃm(0,2,8,10).
#45. For F(A,B,C,D)=ฮฃm(1,3,9,11,5,7,13,15), the minimal SOP is:
#46. When using don’t-care terms in 4-variable K-maps, best practice is to:
#47. A minimized SOP misses a consensus term between adjacent implicants. What issue is most likely in real hardware?
#48. Minimize F(A,B,C,D) = ฮฃm(0,2,8,10).
#49. For F(A,B,C,D)=ฮฃm(1,3,9,11,5,7,13,15), the minimal SOP is:
#50. When using don’t-care terms in 4-variable K-maps, best practice is to:
#51. A minimized SOP misses a consensus term between adjacent implicants. What issue is most likely in real hardware?
#52. Minimize F(A,B,C,D) = ฮฃm(0,2,8,10).
#53. A JK flip-flop with asynchronous clear receives short noisy pulses on clear. Which failure mode is most likely?
#54. Designing a synchronous MOD-10 counter with minimal bits (4) leaves unused states. What is a robust strategy?
#55. Race-around in level-sensitive JK designs is primarily mitigated by:
#56. A synchronous counter fails at high frequency due to long combinational next-state logic. What timing condition is most directly violated?
#57. Two asynchronous inputs enter different flip-flops and reconverge combinationally. Main risk in FSM behavior is:
#58. A JK flip-flop with asynchronous clear receives short noisy pulses on clear. Which failure mode is most likely?
#59. Designing a synchronous MOD-10 counter with minimal bits (4) leaves unused states. What is a robust strategy?
#60. Race-around in level-sensitive JK designs is primarily mitigated by:
#61. A synchronous counter fails at high frequency due to long combinational next-state logic. What timing condition is most directly violated?
#62. Two asynchronous inputs enter different flip-flops and reconverge combinationally. Main risk in FSM behavior is:
#63. A JK flip-flop with asynchronous clear receives short noisy pulses on clear. Which failure mode is most likely?
#64. Designing a synchronous MOD-14 counter with minimal bits (4) leaves unused states. What is a robust strategy?
#65. A Mealy FSM output glitches when inputs change asynchronously near clock edges. Best mitigation is:
#66. An FPGA path has data arrival at 5.8 ns after launch edge and capture clock at 7.0 ns with setup 1.5 ns. Setup slack is:
#67. A hold-time violation is most likely fixed by which action?
#68. State encoding that minimizes simultaneous bit changes between adjacent states helps reduce:
#69. In asynchronous combinational paths, race conditions mainly arise when:
#70. A Mealy FSM output glitches when inputs change asynchronously near clock edges. Best mitigation is:
#71. An FPGA path has data arrival at 5.8 ns after launch edge and capture clock at 7.0 ns with setup 1.5 ns. Setup slack is:
#72. A hold-time violation is most likely fixed by which action?
#73. State encoding that minimizes simultaneous bit changes between adjacent states helps reduce:
#74. In asynchronous combinational paths, race conditions mainly arise when:
#75. A Mealy FSM output glitches when inputs change asynchronously near clock edges. Best mitigation is:
#76. An FPGA path has data arrival at 5.8 ns after launch edge and capture clock at 7.0 ns with setup 1.5 ns. Setup slack is:
#77. A JK flip-flop with asynchronous clear receives short noisy pulses on clear. Which failure mode is most likely?
#78. Designing a synchronous MOD-10 counter with minimal bits (4) leaves unused states. What is a robust strategy?
#79. Race-around in level-sensitive JK designs is primarily mitigated by:
#80. A synchronous counter fails at high frequency due to long combinational next-state logic. What timing condition is most directly violated?
#81. Two asynchronous inputs enter different flip-flops and reconverge combinationally. Main risk in FSM behavior is:
#82. A JK flip-flop with asynchronous clear receives short noisy pulses on clear. Which failure mode is most likely?
#83. Designing a synchronous MOD-12 counter with minimal bits (4) leaves unused states. What is a robust strategy?
#84. Race-around in level-sensitive JK designs is primarily mitigated by:
#85. A synchronous counter fails at high frequency due to long combinational next-state logic. What timing condition is most directly violated?
#86. Two asynchronous inputs enter different flip-flops and reconverge combinationally. Main risk in FSM behavior is:
#87. A JK flip-flop with asynchronous clear receives short noisy pulses on clear. Which failure mode is most likely?
#88. Designing a synchronous MOD-12 counter with minimal bits (4) leaves unused states. What is a robust strategy?
#89. A Mealy FSM output glitches when inputs change asynchronously near clock edges. Best mitigation is:
#90. An FPGA path has data arrival at 5.8 ns after launch edge and capture clock at 7.0 ns with setup 1.5 ns. Setup slack is:
#91. A hold-time violation is most likely fixed by which action?
#92. State encoding that minimizes simultaneous bit changes between adjacent states helps reduce:
#93. In asynchronous combinational paths, race conditions mainly arise when:
#94. A Mealy FSM output glitches when inputs change asynchronously near clock edges. Best mitigation is:
#95. An FPGA path has data arrival at 5.8 ns after launch edge and capture clock at 7.0 ns with setup 1.5 ns. Setup slack is:
#96. A hold-time violation is most likely fixed by which action?
#97. State encoding that minimizes simultaneous bit changes between adjacent states helps reduce:
#98. In asynchronous combinational paths, race conditions mainly arise when:
#99. A Mealy FSM output glitches when inputs change asynchronously near clock edges. Best mitigation is:
#100. An FPGA path has data arrival at 5.8 ns after launch edge and capture clock at 7.0 ns with setup 1.5 ns. Setup slack is:
