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Computer Systems –
Medium Difficulty
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#1. A microprocessor runs at 800 MHz. What is one clock period?
#2. A CPU has CPI=1.1 at 500 MHz. Approximate instruction throughput is:
#3. Which CPU register typically holds the address of the next instruction to execute?
#4. The ALU in a microprocessor primarily performs:
#5. Which architecture uses separate instruction and data paths for potential parallel access?
#6. A microprocessor runs at 800 MHz. What is one clock period?
#7. A CPU has CPI=2 at 500 MHz. Approximate instruction throughput is:
#8. Which CPU register typically holds the address of the next instruction to execute?
#9. The ALU in a microprocessor primarily performs:
#10. Which architecture uses separate instruction and data paths for potential parallel access?
#11. A microprocessor runs at 800 MHz. What is one clock period?
#12. A CPU has CPI=2 at 1000 MHz. Approximate instruction throughput is:
#13. Which CPU register typically holds the address of the next instruction to execute?
#14. The ALU in a microprocessor primarily performs:
#15. Which architecture uses separate instruction and data paths for potential parallel access?
#16. A microprocessor runs at 200 MHz. What is one clock period?
#17. A CPU has CPI=1.5 at 500 MHz. Approximate instruction throughput is:
#18. Which CPU register typically holds the address of the next instruction to execute?
#19. The ALU in a microprocessor primarily performs:
#20. Which architecture uses separate instruction and data paths for potential parallel access?
#21. A microprocessor runs at 400 MHz. What is one clock period?
#22. A CPU has CPI=1.1 at 1500 MHz. Approximate instruction throughput is:
#23. Which CPU register typically holds the address of the next instruction to execute?
#24. The ALU in a microprocessor primarily performs:
#25. Which architecture uses separate instruction and data paths for potential parallel access?
#26. A microprocessor runs at 400 MHz. What is one clock period?
#27. A CPU has CPI=1.5 at 1000 MHz. Approximate instruction throughput is:
#28. Which CPU register typically holds the address of the next instruction to execute?
#29. The ALU in a microprocessor primarily performs:
#30. Which architecture uses separate instruction and data paths for potential parallel access?
#31. A microprocessor runs at 100 MHz. What is one clock period?
#32. A CPU has CPI=2 at 1500 MHz. Approximate instruction throughput is:
#33. Which CPU register typically holds the address of the next instruction to execute?
#34. The ALU in a microprocessor primarily performs:
#35. A byte-addressable memory has 16 address lines. How many bytes can be addressed?
#36. Memory organization is 2048 x 16. What is total capacity in bits?
#37. Which memory is non-volatile and typically used for firmware storage?
#38. Compared with DRAM, SRAM is generally:
#39. A cache block size is 16 bytes. The block offset field needs how many bits?
#40. Given cache hit rate 0.95, hit time 2.0 ns, miss penalty 80 ns, what is AMAT?
#41. A byte-addressable memory has 10 address lines. How many bytes can be addressed?
#42. Memory organization is 4096 x 8. What is total capacity in bits?
#43. Which memory is non-volatile and typically used for firmware storage?
#44. Compared with DRAM, SRAM is generally:
#45. A cache block size is 64 bytes. The block offset field needs how many bits?
#46. Given cache hit rate 0.92, hit time 1.5 ns, miss penalty 60 ns, what is AMAT?
#47. A byte-addressable memory has 12 address lines. How many bytes can be addressed?
#48. Memory organization is 4096 x 16. What is total capacity in bits?
#49. Which memory is non-volatile and typically used for firmware storage?
#50. Compared with DRAM, SRAM is generally:
#51. A cache block size is 64 bytes. The block offset field needs how many bits?
#52. Given cache hit rate 0.95, hit time 2.0 ns, miss penalty 80 ns, what is AMAT?
#53. A byte-addressable memory has 12 address lines. How many bytes can be addressed?
#54. Memory organization is 2048 x 16. What is total capacity in bits?
#55. Which memory is non-volatile and typically used for firmware storage?
#56. Compared with DRAM, SRAM is generally:
#57. A cache block size is 32 bytes. The block offset field needs how many bits?
#58. Given cache hit rate 0.92, hit time 1.5 ns, miss penalty 60 ns, what is AMAT?
#59. A byte-addressable memory has 10 address lines. How many bytes can be addressed?
#60. Memory organization is 4096 x 8. What is total capacity in bits?
#61. Which memory is non-volatile and typically used for firmware storage?
#62. Compared with DRAM, SRAM is generally:
#63. A cache block size is 16 bytes. The block offset field needs how many bits?
#64. Given cache hit rate 0.92, hit time 1.0 ns, miss penalty 60 ns, what is AMAT?
#65. A byte-addressable memory has 10 address lines. How many bytes can be addressed?
#66. Memory organization is 2048 x 16. What is total capacity in bits?
#67. Which memory is non-volatile and typically used for firmware storage?
#68. DMA improves I/O performance mainly by:
#69. In interrupt-driven I/O, an interrupt service routine (ISR) should generally be:
#70. A synchronous bus runs at 50 MHz and inserts 1 wait states per transfer. What is transfer cycle time?
#71. Memory-mapped I/O differs from isolated I/O because:
#72. What is the purpose of handshaking signals in asynchronous interfacing?
#73. DMA improves I/O performance mainly by:
#74. In interrupt-driven I/O, an interrupt service routine (ISR) should generally be:
#75. A synchronous bus runs at 200 MHz and inserts 3 wait states per transfer. What is transfer cycle time?
#76. Memory-mapped I/O differs from isolated I/O because:
#77. What is the purpose of handshaking signals in asynchronous interfacing?
#78. DMA improves I/O performance mainly by:
#79. In interrupt-driven I/O, an interrupt service routine (ISR) should generally be:
#80. A synchronous bus runs at 100 MHz and inserts 3 wait states per transfer. What is transfer cycle time?
#81. Memory-mapped I/O differs from isolated I/O because:
#82. What is the purpose of handshaking signals in asynchronous interfacing?
#83. DMA improves I/O performance mainly by:
#84. In interrupt-driven I/O, an interrupt service routine (ISR) should generally be:
#85. A synchronous bus runs at 200 MHz and inserts 0 wait states per transfer. What is transfer cycle time?
#86. Memory-mapped I/O differs from isolated I/O because:
#87. What is the purpose of handshaking signals in asynchronous interfacing?
#88. DMA improves I/O performance mainly by:
#89. In interrupt-driven I/O, an interrupt service routine (ISR) should generally be:
#90. A synchronous bus runs at 200 MHz and inserts 2 wait states per transfer. What is transfer cycle time?
#91. Memory-mapped I/O differs from isolated I/O because:
#92. What is the purpose of handshaking signals in asynchronous interfacing?
#93. DMA improves I/O performance mainly by:
#94. In interrupt-driven I/O, an interrupt service routine (ISR) should generally be:
#95. A synchronous bus runs at 50 MHz and inserts 3 wait states per transfer. What is transfer cycle time?
#96. Memory-mapped I/O differs from isolated I/O because:
#97. What is the purpose of handshaking signals in asynchronous interfacing?
#98. DMA improves I/O performance mainly by:
#99. In interrupt-driven I/O, an interrupt service routine (ISR) should generally be:
#100. A synchronous bus runs at 50 MHz and inserts 2 wait states per transfer. What is transfer cycle time?
