#1. A pipelined CPU has base CPI 1.2 and average stall cycles/instruction 0.2. Effective CPI is:
#2. For a classic 5-stage pipeline, which hazard occurs when an instruction needs a result not yet written by a prior instruction?
#3. Branch mispredictions in deep pipelines mainly increase:
#4. Out-of-order execution can improve throughput primarily by:
#5. A processor with forwarding still stalls on load-use dependency. Why?
#6. A pipelined CPU has base CPI 1.2 and average stall cycles/instruction 0.4. Effective CPI is:
#7. For a classic 5-stage pipeline, which hazard occurs when an instruction needs a result not yet written by a prior instruction?
#8. Branch mispredictions in deep pipelines mainly increase:
#9. Out-of-order execution can improve throughput primarily by:
#10. A processor with forwarding still stalls on load-use dependency. Why?
#11. A pipelined CPU has base CPI 1.2 and average stall cycles/instruction 0.2. Effective CPI is:
#12. For a classic 5-stage pipeline, which hazard occurs when an instruction needs a result not yet written by a prior instruction?
#13. Branch mispredictions in deep pipelines mainly increase:
#14. Out-of-order execution can improve throughput primarily by:
#15. A processor with forwarding still stalls on load-use dependency. Why?
#16. A pipelined CPU has base CPI 1.2 and average stall cycles/instruction 0.6. Effective CPI is:
#17. For a classic 5-stage pipeline, which hazard occurs when an instruction needs a result not yet written by a prior instruction?
#18. Branch mispredictions in deep pipelines mainly increase:
#19. Out-of-order execution can improve throughput primarily by:
#20. A processor with forwarding still stalls on load-use dependency. Why?
#21. A pipelined CPU has base CPI 1.2 and average stall cycles/instruction 0.6. Effective CPI is:
#22. For a classic 5-stage pipeline, which hazard occurs when an instruction needs a result not yet written by a prior instruction?
#23. Branch mispredictions in deep pipelines mainly increase:
#24. Out-of-order execution can improve throughput primarily by:
#25. A processor with forwarding still stalls on load-use dependency. Why?
#26. A pipelined CPU has base CPI 1.5 and average stall cycles/instruction 0.4. Effective CPI is:
#27. For a classic 5-stage pipeline, which hazard occurs when an instruction needs a result not yet written by a prior instruction?
#28. Branch mispredictions in deep pipelines mainly increase:
#29. Out-of-order execution can improve throughput primarily by:
#30. A processor with forwarding still stalls on load-use dependency. Why?
#31. A pipelined CPU has base CPI 1 and average stall cycles/instruction 0.6. Effective CPI is:
#32. For a classic 5-stage pipeline, which hazard occurs when an instruction needs a result not yet written by a prior instruction?
#33. Branch mispredictions in deep pipelines mainly increase:
#34. Out-of-order execution can improve throughput primarily by:
#35. A 32-bit cache has 512 sets, 4-way associativity, and 32-byte blocks. Tag bits per line are:
#36. For two-level cache, AMAT = L1_hit_time + L1_miss_rate*(L2_hit_time + L2_miss_rate*Memory). Compute AMAT for given values.
#37. Increasing cache associativity usually reduces conflict misses but may also:
#38. Write-back caches compared with write-through caches typically:
#39. A system suffers many TLB misses after page-table growth. Which effect is most likely?
#40. In virtual memory systems, page faults are expensive primarily because they may require:
#41. A 32-bit cache has 128 sets, 2-way associativity, and 32-byte blocks. Tag bits per line are:
#42. For two-level cache, AMAT = L1_hit_time + L1_miss_rate*(L2_hit_time + L2_miss_rate*Memory). Compute AMAT for given values.
#43. Increasing cache associativity usually reduces conflict misses but may also:
#44. Write-back caches compared with write-through caches typically:
#45. A system suffers many TLB misses after page-table growth. Which effect is most likely?
#46. In virtual memory systems, page faults are expensive primarily because they may require:
#47. A 32-bit cache has 128 sets, 4-way associativity, and 32-byte blocks. Tag bits per line are:
#48. For two-level cache, AMAT = L1_hit_time + L1_miss_rate*(L2_hit_time + L2_miss_rate*Memory). Compute AMAT for given values.
#49. Increasing cache associativity usually reduces conflict misses but may also:
#50. Write-back caches compared with write-through caches typically:
#51. A system suffers many TLB misses after page-table growth. Which effect is most likely?
#52. In virtual memory systems, page faults are expensive primarily because they may require:
#53. A 32-bit cache has 64 sets, 1-way associativity, and 32-byte blocks. Tag bits per line are:
#54. For two-level cache, AMAT = L1_hit_time + L1_miss_rate*(L2_hit_time + L2_miss_rate*Memory). Compute AMAT for given values.
#55. Increasing cache associativity usually reduces conflict misses but may also:
#56. Write-back caches compared with write-through caches typically:
#57. A system suffers many TLB misses after page-table growth. Which effect is most likely?
#58. In virtual memory systems, page faults are expensive primarily because they may require:
#59. A 32-bit cache has 128 sets, 2-way associativity, and 64-byte blocks. Tag bits per line are:
#60. For two-level cache, AMAT = L1_hit_time + L1_miss_rate*(L2_hit_time + L2_miss_rate*Memory). Compute AMAT for given values.
#61. Increasing cache associativity usually reduces conflict misses but may also:
#62. Write-back caches compared with write-through caches typically:
#63. A system suffers many TLB misses after page-table growth. Which effect is most likely?
#64. In virtual memory systems, page faults are expensive primarily because they may require:
#65. A 32-bit cache has 512 sets, 1-way associativity, and 64-byte blocks. Tag bits per line are:
#66. For two-level cache, AMAT = L1_hit_time + L1_miss_rate*(L2_hit_time + L2_miss_rate*Memory). Compute AMAT for given values.
#67. Increasing cache associativity usually reduces conflict misses but may also:
#68. A burst transfer sends 4 words of 64 bits each on a 100 MHz bus, one word per cycle. What is theoretical burst data rate?
#69. An interrupt controller supports priority levels. What configuration best reduces worst-case latency for critical control-loop ISR?
#70. A peripheral crosses into CPU clock domain asynchronously. Best practice is to use:
#71. Bus arbitration starvation under heavy DMA load is observed. Which fix is most appropriate?
#72. A memory-mapped peripheral register must be accessed exactly as programmed. Compiler optimization causes missing reads. What software-side control is required?
#73. A burst transfer sends 8 words of 32 bits each on a 66 MHz bus, one word per cycle. What is theoretical burst data rate?
#74. An interrupt controller supports priority levels. What configuration best reduces worst-case latency for critical control-loop ISR?
#75. A peripheral crosses into CPU clock domain asynchronously. Best practice is to use:
#76. Bus arbitration starvation under heavy DMA load is observed. Which fix is most appropriate?
#77. A memory-mapped peripheral register must be accessed exactly as programmed. Compiler optimization causes missing reads. What software-side control is required?
#78. A burst transfer sends 16 words of 32 bits each on a 50 MHz bus, one word per cycle. What is theoretical burst data rate?
#79. An interrupt controller supports priority levels. What configuration best reduces worst-case latency for critical control-loop ISR?
#80. A peripheral crosses into CPU clock domain asynchronously. Best practice is to use:
#81. Bus arbitration starvation under heavy DMA load is observed. Which fix is most appropriate?
#82. A memory-mapped peripheral register must be accessed exactly as programmed. Compiler optimization causes missing reads. What software-side control is required?
#83. A burst transfer sends 8 words of 32 bits each on a 66 MHz bus, one word per cycle. What is theoretical burst data rate?
#84. An interrupt controller supports priority levels. What configuration best reduces worst-case latency for critical control-loop ISR?
#85. A peripheral crosses into CPU clock domain asynchronously. Best practice is to use:
#86. Bus arbitration starvation under heavy DMA load is observed. Which fix is most appropriate?
#87. A memory-mapped peripheral register must be accessed exactly as programmed. Compiler optimization causes missing reads. What software-side control is required?
#88. A burst transfer sends 8 words of 32 bits each on a 100 MHz bus, one word per cycle. What is theoretical burst data rate?
#89. An interrupt controller supports priority levels. What configuration best reduces worst-case latency for critical control-loop ISR?
#90. A peripheral crosses into CPU clock domain asynchronously. Best practice is to use:
#91. Bus arbitration starvation under heavy DMA load is observed. Which fix is most appropriate?
#92. A memory-mapped peripheral register must be accessed exactly as programmed. Compiler optimization causes missing reads. What software-side control is required?
#93. A burst transfer sends 8 words of 64 bits each on a 50 MHz bus, one word per cycle. What is theoretical burst data rate?
#94. An interrupt controller supports priority levels. What configuration best reduces worst-case latency for critical control-loop ISR?
#95. A peripheral crosses into CPU clock domain asynchronously. Best practice is to use:
#96. Bus arbitration starvation under heavy DMA load is observed. Which fix is most appropriate?
#97. A memory-mapped peripheral register must be accessed exactly as programmed. Compiler optimization causes missing reads. What software-side control is required?
#98. A burst transfer sends 4 words of 64 bits each on a 100 MHz bus, one word per cycle. What is theoretical burst data rate?
#99. An interrupt controller supports priority levels. What configuration best reduces worst-case latency for critical control-loop ISR?
#100. A peripheral crosses into CPU clock domain asynchronously. Best practice is to use:
